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1/4 STRUCTURE TYPE PRODUCT SERIES FEATURES Silicon Monolithic Integrated Circuit 1ch DC/DC converter IC
BD95503MUV
3 Built in 1ch H Reg DC/DC converter controller Adjustable output voltage setting (0.75V5.5V)
Absolute Maximum Ratings (Ta=25) Parameter Input Voltage BOOT Voltage BOOT-SW Voltage Output Voltage Output Feedback Voltage VREG Voltage Current Limit Setting Voltage Logic Input Voltage Output CurrentAverage Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature
Symbol VIN, VINS BOOT BOOT-SW VOUT FB VREG ILIM EN Isw Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax
Limit 24 30 7 7 7 24
1*2 1*2 1*2 1*2
Unit V V V V V V V V A W W W W
VREG
1*2
VREG
1*2
31 0.34 0.70 1.21 3.56
3 4 5 6
-20+100 -55+150 +150
*1 Not to exceed Pd. *2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle. *3 Reduced by 2.7mW/ for each increase in Ta of 1 over 25 (when don't mounted on a heat radiation board ) 2 *4 Reduced by 5.6mW/ for increase in Ta of 1 over 25. (when mounted on a board 74.2mmx74.2mmx1.6mm Glass-epoxy PCB, copper foil area : 10.29mm ) *5 Reduced by 9.7mW/ for increase in Ta of 1 over 25. (when mounted on a board 74.2mmx74.2mmx1.6mm Glass-epoxy PCB, copper foil area: 10.29mm2, 2-3layer: 5505mm2) 2 *6 Reduced by 28.5mW/ for increase in Ta of 1 over 25. (when mounted on a board 74.2mmx74.2mmx1.6mm Glass-epoxy PCB, copper foil area: 5505mm )
Operating Conditions Ta=25 Parameter Input Voltage BOOT Voltage SW Voltage BOOT-SW Voltage Logic Input Voltage Output Voltage MIN ON TIME
Symbol VIN, VINS BOOT SW BOOT-SW EN VOUT tonmin
MIN. 7.5 4.5 -0.7 4.5 0 0.75 -
MAX. 20 25 20 5.5 20 5.5 100
Unit V V V V V V ns
This product is not designed to be used in a radioactive environment.
REV. B
2/4 Electrical Characteristics (Unless otherwise noted, Ta=25 VCC=5V, VIN=VINS=12V, VEN=3V, VOUT=1.8V) Standard Value Parameter Symbol Unit Conditions MIN. TYP. MAX. [Whole Device] VIN Bias current IIN 1.0 2.0 mA VCC=VREG VIN Standby current IIN_stb 0 10 A VEN=0V EN Low Voltage VEN_low GND 0.3 V EN High Voltage VEN_high 2.2 20 V EN Pull-down resistance REN 30 50 70 k [5VLinear Regulator] VREG Standby Voltage VREG_stb 0.1 V VEN=0V VREG Output Voltage [Under Voltage Lock Out] VREG threshold Voltage VREG hysteresis Voltage [Over Voltage Protection] FB threshold Voltage [H3RegTM Control] ON Time MIN OFF Time [FET Driver] High side ON resistance Low side ON resistance [Current Control] Current Limit threshold Voltage [Output Voltage Sense] FB threshold Voltage FB Input current VOUT discharge current [SCP] Threshold Voltage VREG VREG_UVLO dVREG_UVLO FB_OVP ton Toffmin RHGhon RLGlon Vilim FB IFB IVOUT Vthscp 4.9 3.75 100 0.8 200 300 440 0.738 -1 5 REFx0.6 5.1 4.20 160 0.9 300 500 0.270 0.135 470 0.750 10 REFx0.7 5.3 4.65 220 1.0 400 0.540 0.270 500 0.762 1 REFx0.8 V
VIN=VINS=7.5V to 20V Ireg=10mA
V VREG:Sweep up mV VREG:Sweep down V ns ns
mV RILIM=47k V A mA VOUT=1V, VEN=0V V
REV. B
3/4 Block Diagram
VIN
VINS
7 6
VREG
VREG
VIN
8 12
VOUT VOUT
1
Thermal Protection
TSD
VIN BOOT
EN/UVLO TSD/OVP
5VReg
5V
23
18
SW
VOUT
EN
Soft Start
SS REF SS
H Reg Controller Block
+ +
3
TM
Driver R S Q SW OCP Circuit
VREG
22
FB
2
-
OVP UVLO OCP SCP TSD
13 17
PGND
VREG
ILIM VCC
4 5
EN/UVLO REF(=0.75V) BG UVLO OVP SCP Delay
+ + REFx0.7 FB 0.9V FB
EN
24
Reference Block
EN/UVLO
3
GND
Physical Dimension
Pin numberPin name
PIN No. 1 2 3 4 5 6 7
Lot No. 1 PIN mark
95503
8-12 13-17 18-22 23 24 Reverse
PIN name VOUT FB GND ILIM VCC VREG VINS VIN PGND SW BOOT EN FIN
(Unit : mm)
REV. B
4/4 NOTE FOR USE
1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. Supply line Since the motor's reverse electromotive force gives rise to the return of regenerative current, measures should be taken to establish a channel for the current, such as adding a capacitor between the power supply and GND. In determining the approach to take, make sure that no problems will be posed by the various characteristics involved, such as capacitance loss at low temperatures with an electrolytic capacitor. 3. GND voltage The potential of GND, PGND pin must be minimum potential in all operating conditions. 4. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 5. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 6. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 7. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 8. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 9. Electrical characteristics The electrical characteristics in the Specifications may vary depending on ambient temperature, power supply voltage, circuit(s) externally applied, and/or other conditions. It is therefore requested to carefully check them including transient characteristics. 10. Not of a radiation-resistant design. OUTPUT 11. In the event that load containing a large inductance component PIN is connected to the output terminal, and generation of back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode. 12. Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Pin A
Resistor
Pin A N
Pin B
C
B E
Transistor (NPN)
Pin B
N P P N Parasitic element
N
P
P
N P P N
B
C E Parasitic element
P substrate Parasitic element GND Parasitic element
P substrate GND GND GND
Other adjacent elements
13. Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. 14. Operating ranges If it is within the operating ranges, certain circuit functions and operations are warranted in the working ambient temperature range. With respect to characteristic values, it is unable to warrant standard values of electric characteristics but there are no sudden variations in characteristic values within these ranges. 15. Thermal shutdown circuit This IC is provided with a built-in thermal shutdown (TSD) circuit, which is activated when the chip temperature reaches the threshold value listed below. When TSD is on, the device goes to high impedance mode. Note that the TSD circuit is provided for the exclusive purpose shutting down the IC in the presence of extreme heat, and is not designed to protect the IC per se or guarantee performance when or after extreme heat conditions occur. Therefore, do not operate the IC with the expectation of continued use or subsequent operation once the TSD is activated. TSD ON temperature [] (typ.) Hysteresis temperature[] (typ.) 175 15 16.Output Voltage Resistor Setting Output volage is adjusted with resistor. Total 10kohm resistor is recommended so that the output voltage is not affected by the FB input current (Typ. 1uA). 17. Heat sink (FIN) Since the heat sink (FIN) is connected with the Sub, short it to the GND.
REV. B
Notice
Notes
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